GEM_TSU_REF_CTRL (CRL_APB) Register Description
Register Name | GEM_TSU_REF_CTRL |
---|---|
Offset Address | 0x0000000100 |
Absolute Address | 0x00FF5E0100 (CRL_APB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00051000 |
Description | GEM TimeStamp Clock Generator Control. |
GEM_TSU_REF_CTRL (CRL_APB) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:25 | rwNormal read/write | 0x0 | reserved |
CLKACT | 24 | rwNormal read/write | 0x0 | Clock active control. 0: disable. Clock stop. 1: enable. |
Reserved | 23:22 | rwNormal read/write | 0x0 | reserved |
DIVISOR1 | 21:16 | rwNormal read/write | 0x5 | 6-bit divider. |
Reserved | 15:14 | rwNormal read/write | 0x0 | reserved |
DIVISOR0 | 13:8 | rwNormal read/write | 0x10 | 6-bit divider. |
Reserved | 7:3 | rwNormal read/write | 0x0 | reserved |
SRCSEL | 2:0 | rwNormal read/write | 0x0 | Clock generator input source. 000: IOPLL 010: RPLL 011: DPLL_CLK_TO_LPD |