GICC_AEOIR (GIC400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICC_AEOIR (GIC400) Register Description

Register NameGICC_AEOIR
Offset Address0x0000020024
Absolute Address 0x00F9020024 (ACPU_GIC)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionAliased End of Interrupt Register

GICC_AEOIR (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0woWrite-only0Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.