GICC_IAR (GIC400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICC_IAR (GIC400) Register Description

Register NameGICC_IAR
Offset Address0x000002000C
Absolute Address 0x00F902000C (ACPU_GIC)
Width32
TyperoRead-only
Reset Value0x000003FF
DescriptionInterrupt Acknowledge Register

GICC_IAR (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0roRead-only0x3FFRefer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.