GICC_NSAPR0 (GIC400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICC_NSAPR0 (GIC400) Register Description

Register NameGICC_NSAPR0
Offset Address0x00000200E0
Absolute Address 0x00F90200E0 (ACPU_GIC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionNon-Secure Active Priority Register

GICC_NSAPR0 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0rwNormal read/write0x0Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.