GICD_CIDR3 (GIC400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICD_CIDR3 (GIC400) Register Description

Register NameGICD_CIDR3
Offset Address0x0000010FFC
Absolute Address 0x00F9010FFC (ACPU_GIC)
Width32
TyperoRead-only
Reset Value0x000000B1
DescriptionComponent ID3 Register

GICD_CIDR3 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0roRead-only0xB1Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.