GICD_ICFGR0 (GIC400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICD_ICFGR0 (GIC400) Register Description

Register NameGICD_ICFGR0
Offset Address0x0000010C00
Absolute Address 0x00F9010C00 (ACPU_GIC)
Width32
TyperoRead-only
Reset Value0xAAAAAAAA
DescriptionInterrupt Configuration Registers

GICD_ICFGR0 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0roRead-only0xAAAAAAAARefer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.