GICD_ICFGR5 (GIC400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICD_ICFGR5 (GIC400) Register Description

Register NameGICD_ICFGR5
Offset Address0x0000010C14
Absolute Address 0x00F9010C14 (ACPU_GIC)
Width32
TyperwNormal read/write
Reset Value0x55555555
DescriptionInterrupt Configuration Registers

GICD_ICFGR5 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0rwNormal read/write0x55555555Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.