GICD_PIDR1 (GIC400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICD_PIDR1 (GIC400) Register Description

Register NameGICD_PIDR1
Offset Address0x0000010FE4
Absolute Address 0x00F9010FE4 (ACPU_GIC)
Width32
TyperoRead-only
Reset Value0x000000B4
DescriptionPeripheral ID1 Register

GICD_PIDR1 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0roRead-only0xB4Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.