GICH_ELSR0_Alias5 (GIC400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICH_ELSR0_Alias5 (GIC400) Register Description

Register NameGICH_ELSR0_Alias5
Offset Address0x0000050A30
Absolute Address 0x00F9050A30 (ACPU_GIC)
Width32
TyperoRead-only
Reset Value0x0000000F
DescriptionEmpty List register Status Register

GICH_ELSR0_Alias5 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0roRead-only0xFRefer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.