GICH_LR0_Alias5 (GIC400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICH_LR0_Alias5 (GIC400) Register Description

Register NameGICH_LR0_Alias5
Offset Address0x0000050B00
Absolute Address 0x00F9050B00 (ACPU_GIC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionList Register 0

GICH_LR0_Alias5 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0rwNormal read/write0x0Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.