GICH_MISR (GIC400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICH_MISR (GIC400) Register Description

Register NameGICH_MISR
Offset Address0x0000040010
Absolute Address 0x00F9040010 (ACPU_GIC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionMaintenance Interrupt Status Register

GICH_MISR (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0roRead-only0x0Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.