GICV_AIAR (GIC400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICV_AIAR (GIC400) Register Description

Register NameGICV_AIAR
Offset Address0x0000060020
Absolute Address 0x00F9060020 (ACPU_GIC)
Width32
TyperoRead-only
Reset Value0x000003FF
DescriptionVM Aliased Interrupt Acknowledge Register

GICV_AIAR (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0roRead-only0x3FFRefer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.