GLOBAL_CNTRL (PMU_GLOBAL) Register Description
| Register Name | GLOBAL_CNTRL |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address | 0x00FFD80000 (PMU_GLOBAL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00008800 |
| Description | PMU control and status register. |
Wakeup, SLVERR signal, Coherency, Firmware loaded, QoS, PMU activity state.
GLOBAL_CNTRL (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:17 | roRead-only | 0x0 | reserved |
| MB_Sleep | 16 | roRead-only | 0x0 | PMU processing mode: 0: active. 1: sleep. Read-only. |
| Write_QOS | 15:12 | rwNormal read/write | 0x8 | QoS regulator setting used by PMU for AXI Write requests. 4-bit read/write. |
| Read_QOS | 11:8 | rwNormal read/write | 0x8 | QoS regulator setting used by PMU for AXI Read requests. 4-bit read/write. |
| Reserved | 7:5 | roRead-only | 0x0 | reserved |
| FW_Is_Present | 4 | rwNormal read/write | 0x0 | Software sets this bit to indicate that the PMU firmware has been loaded in the PMU RAM. 0: not loaded. 1: loaded. After the firmware is loaded, the software can call its service routines. |
| Reserved | 3 | roRead-only | 0x0 | reserved |
| Coherent | 2 | rwNormal read/write | 0x0 | PMU coherency with APU setting. 0: outside of APU coherency. 1: coherent using the legacy ACP port on the APU. |
| SLVERR_Enable | 1 | rwNormal read/write | 0x0 | Enable the SLVERR error signal back to the interconnect when a Register Access Error occurs. 0: disable error signal. 1: assert error signal; write data is ignored and reads returns 0. |
| Dont_Sleep | 0 | rwNormal read/write | 0x0 | PMU wake-up when the PMU is in sleep mode and the interrupts are disabled. 0: no signal. 1: assert wake up signal. This feature is used after the PMU firmware is loaded into RAM. |