GPR0 (DDR_PHY) Register Description
| Register Name | GPR0 |
|---|---|
| Offset Address | 0x00000000C0 |
| Absolute Address | 0x00FD0800C0 (DDR_PHY) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | General Purpose Register 0 |
GPR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| GPR0 | 31:1 | rwNormal read/write | 0x0 | General Purpose Register 0: General purpose register bits. |
| WDQSEXT | 0 | rwNormal read/write | 0x0 | Write DQS Extension mode: If set, enables support for LPDDR4 WDQS Control. This feature is required by some DRAM vendors. Valid values are: 0 = WDQS Control disabled 1 = WDQS Control Mode 1 enabled |