GPU_REF_CTRL (CRF_APB) Register Description
| Register Name | GPU_REF_CTRL |
|---|---|
| Offset Address | 0x0000000084 |
| Absolute Address | 0x00FD1A0084 (CRF_APB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00001500 |
| Description | GPU Clock Generator Control. |
GPU_REF_CTRL (CRF_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PP1_CLKACT | 26 | rwNormal read/write | 0x0 | Clock active control for Pixel Processor 1. 0: disable. 1: enable. |
| PP0_CLKACT | 25 | rwNormal read/write | 0x0 | Clock active control for Pixel Processor 0. 0: disable. 1: enable. |
| CLKACT | 24 | rwNormal read/write | 0x0 | Clock active control for GPU and both Pixel Processors. 0: disable. 1: enable. |
| DIVISOR0 | 13:8 | rwNormal read/write | 0x15 | 6-bit divider. |
| SRCSEL | 2:0 | rwNormal read/write | 0x0 | Clock generator input source. 000: IOPLL_TO_FPD 010: VPLL 011: DPLL |