HEEXTMUXR (STM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

HEEXTMUXR (STM) Register Description

Register NameHEEXTMUXR
Offset Address0x0000000D68
Absolute Address 0x00FE9C0D68 (CORESIGHT_SOC_STM)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionControl hardware event multiplexors external to STM.

HEEXTMUXR (STM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
EXTMUX 7:0rwNormal read/write0Specifies the value that the optional external multiplexing logic uses to select the hardware events to connect to the STM. The value of this register is an output from the STM on the HEEXTMUX[7:0] signals. The behavior of the multiplexing logic is IMPLEMENTATION DEFINED. This field is reset to zero.