HEFEAT1R (STM) Register Description
| Register Name | HEFEAT1R |
|---|---|
| Offset Address | 0x0000000DF8 |
| Absolute Address | 0x00FE9C0DF8 (CORESIGHT_SOC_STM) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Read the features of the STM. |
HEFEAT1R (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| HEEXTMUXSIZE | 30:28 | roRead-only | 0 | Size of Hardware Event external multiplex signals: 3h. |
| NUMHE | 23:15 | roRead-only | 0x0 | The number of hardware events supported by the STM: 40h. |
| HECOMP | 5:4 | roRead-only | 0x0 | Data compression on hardware event tracing support. 3h. |
| HEMASTR | 3 | roRead-only | 0x0 | STMHEMASTR support: 0: |
| HEERR | 2 | roRead-only | 0x0 | Hardware event error detection support: 1: implemented |
| HETER | 0 | roRead-only | 0x0 | STMHETER support: 1: implemented |