HEMASTR (STM) Register Description
| Register Name | HEMASTR |
|---|---|
| Offset Address | 0x0000000DF4 |
| Absolute Address | 0x00FE9C0DF4 (CORESIGHT_SOC_STM) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Master Number in Event Trace |
Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2.
HEMASTR (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| MASTER | 15:0 | roRead-only | 0x0 | The STPv2 master number for hardware event trace: 80h: master number. |