HEMCR (STM) Register Description
| Register Name | HEMCR |
|---|---|
| Offset Address | 0x0000000D64 |
| Absolute Address | 0x00FE9C0D64 (CORESIGHT_SOC_STM) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Control the primary functions of Hardware Event tracing. |
HEMCR (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ATBTRIGEN | 7 | rwNormal read/write | 0x0 | When set, this bit enables the STM to use the ATID value of 0x7D when a Trigger Event on match using STMHETER occurs: 0: disable. 1: enable. |
| TRIGCLEAR | 6 | woWrite-only | 0 | When TRIGCTL indicates single-shot mode, this bit is used to clear TRIGSTATUS.Writing a b1 to this bit when in multi-shot mode is Unpredictable. |
| TRIGSTATUS | 5 | roRead-only | 0 | When TRIGCTL indicates single-shot mode, this indicates whether the single trigger has occurred: |
| TRIGCTL | 4 | rwNormal read/write | 0x0 | Trigger Control: 0: multi-shot. 1: single-shot. |
| ERRDETECT | 2 | roRead-only | 0 | Enable error detection on the hardware event tracing |
| COMPEN | 1 | rwNormal read/write | 0 | Enable leading zero suppression of hardware event data values in the trace stream |
| EN | 0 | rwNormal read/write | 0x0 | Enable Hardware Event tracing: 0: disable. 1: enable. |