HWLPCTL (DDRC) Register Description
| Register Name | HWLPCTL |
|---|---|
| Offset Address | 0x0000000038 |
| Absolute Address | 0x00FD070038 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000003 |
| Description | Hardware Low Power Control Register |
All register fields are static, unless described otherwise in the register field description. Static registers can only be written when the controller is in reset.
HWLPCTL (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| hw_lp_idle_x32 | 27:16 | rwNormal read/write | 0x0 | Hardware idle period. The cactive_ddrc output is driven low if the system is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The hardware idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. |
| hw_lp_exit_idle_en | 1 | rwNormal read/write | 0x1 | When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power Interface and/or Software (PWRCTL.selfref_sw). |
| hw_lp_en | 0 | rwNormal read/write | 0x1 | Enable for Hardware Low Power Interface. Programming Mode: Quasi-dynamic Group 3 |