IDR0 (A53_ETM_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

IDR0 (A53_ETM_2) Register Description

Register NameIDR0
Offset Address0x00000001E0
Absolute Address 0x00FEE401E0 (CORESIGHT_A53_ETM_2)
Width32
TyperoRead-only
Reset Value0x28000EA0
DescriptionID Register 0

IDR0 (A53_ETM_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
COMMOPT29roRead-only0x1Conditional instruction tracing support bit. Indicates if the trace unit supports conditional instruction tracing
TSSIZE28:24roRead-only0x8Global timestamp size field.
QSUPP16:15roRead-only0x0Q element are not supported
QFILT14roRead-only0x0Q element filtering is not supported
CONDTYPE13:12roRead-only0x0Conditional tracing are not supported
NUMEVENT11:10roRead-only0x3Four events are supported
RETSTACK 9roRead-only0x1Return stack implemented
TRCCCI 7roRead-only0x1Cycle counting instruction bit. Indicates if the trace unit supports cycle counting for instructions
TRCCOND 6roRead-only0x0Conditional instruction tracing support bit. Indicates if the trace unit supports conditional instruction tracing
TRCBB 5roRead-only0x1Branch broadcast tracing support bit. Indicates if the trace unit supports branch broadcast tracing
TRCDATA 4:3roRead-only0x0Conditional tracing field.
INSTP0 2:1roRead-only0x0P0 tracing support field.