IDR2 (A53_ETM_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

IDR2 (A53_ETM_0) Register Description

Register NameIDR2
Offset Address0x00000001E8
Absolute Address 0x00FEC401E8 (CORESIGHT_A53_ETM_0)
Width32
TyperoRead-only
Reset Value0x00000488
DescriptionID Register 2

IDR2 (A53_ETM_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CCSIZE28:25roRead-only0x0Indicates the size of the cycle counter in bits minus 12.and so on up to 0b1000, indicating the cycle counter is 20 bits in length.All other values are reserved.If cycle counting is not implemented, as indicated by IDR0., this field is 0b0000.
DVSIZE24:20roRead-only0x0Indicates the data value size in bytes.
DASIZE19:15roRead-only0x0Indicates the data address size in bytes.
VMIDSIZE14:10roRead-only0x1Indicates the VMID size.
CIDSIZE 9:5roRead-only0x4Indicates the Context ID size.
IASIZE 4:0roRead-only0x8Indicates the instruction address size.