IDR3 (A53_ETM_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

IDR3 (A53_ETM_0) Register Description

Register NameIDR3
Offset Address0x00000001EC
Absolute Address 0x00FEC401EC (CORESIGHT_A53_ETM_0)
Width32
TyperoRead-only
Reset Value0x0D7B0004
DescriptionID Register 3

IDR3 (A53_ETM_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
NOOVERFLOW31roRead-only0x0Indicates if NOOVERFLOW is supported
NUMPROC30:28roRead-only0x0Indicates the number of processors available for tracing.
SYSSTALL27roRead-only0x1Indicates if the implementation can support stall control.
STALLCTL26roRead-only0x1Indicates if
is supported
SYNCPR25roRead-only0x0Indicates if an implementation has a fixed synchronization period
TRCERR24roRead-only0x1Indicates if VICTLR.TRCERR is supported
EXLEVEL_NS23:20roRead-only0x7In Non-secure state, each bit indicates whether instruction tracing is supported for the corresponding exception level
EXLEVEL_S19:16roRead-only0xBIn Secure state, each bit indicates whether instruction tracing is supported for the corresponding exception level
CCITMIN11:0roRead-only0x4Indicates the minimum value that can be programmed in THRESHOLD