IDR_0 (CCI_REG) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

IDR_0 (CCI_REG) Register Description

Register Name	IDR_0
Offset Address	0x000000001C
Absolute Address	0x00FD5E001C (CCI_REG)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000000
Description	Interrupt Disable Register. A write of 1 to this location will mask the interrupt

IDR_0 (CCI_REG) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
addr_decode_err	31	woWrite-only	0x0	Address Decode Error
Reserved	30:6	roRead-only	0x0	Reserved
ccnt_oflw	5	woWrite-only	0x0	Interrupt Disable for ccnt_oflw interrupt.
ec3_oflw	4	woWrite-only	0x0	Interrupt Disable for ec3_oflw interrupt.
ec2_oflw	3	woWrite-only	0x0	Interrupt Disable for ec2_oflw interrupt.
ec1_oflw	2	woWrite-only	0x0	Interrupt Disable for ec1_oflw interrupt.
ec0_oflw	1	woWrite-only	0x0	Interrupt Disable for ec0_oflw interrupt.
errorirq	0	woWrite-only	0x0	Interrupt Disable for errorirq interrupt.