ID_AA64ISAR0_EL1_31to0 (A53_DBG_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ID_AA64ISAR0_EL1_31to0 (A53_DBG_1) Register Description

Register NameID_AA64ISAR0_EL1_31to0
Offset Address0x0000000D30
Absolute Address 0x00FED10D30 (CORESIGHT_A53_DBG_1)
Width32
TyperoRead-only
Reset Value0x00011120
DescriptionInstruction Set Attribute Register 0 (low word)

ID_AA64ISAR0_EL1_31to0 (A53_DBG_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CRC3219:16roRead-only0x1CRC32 instructions in AArch64. Possible values of this field are:All other values are reserved.This field must have the same value as ID_ISAR5.CRC32. The architecture requires that if CRC32 is supported in one Execution state, it must be supported in both Execution states.
SHA215:12roRead-only0x1SHA2 instructions in AArch64. Possible values of this field are:All other values are reserved.
SHA111:8roRead-only0x1SHA1 instructions in AArch64. Possible values of this field are:All other values are reserved.
AES 7:4roRead-only0x2AES instructions in AArch64. Possible values of this field are: