ID_DFR0 (R5_DBG_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ID_DFR0 (R5_DBG_0) Register Description

Register NameID_DFR0
Offset Address0x0000000D28
Absolute Address 0x00FEBF0D28 (CORESIGHT_R5_DBG_0)
Width32
TyperoRead-only
Reset Value0x00010400
DescriptionDebug Feature Register 0

ID_DFR0 (R5_DBG_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
uCtlr_debug_model_mmap23:20roRead-only0x0Indicates support for the microcontroller debug model - memory mapped: 0x0= no support.
Trace_debug_model_mmap19:16roRead-only0x1Indicates support for the trace debug model - memory mapped: 0x1= trace supported, memory mapped access.
Trace_debug_model_cp15:12roRead-only0x0Indicates support for the trace debug model - coprocessor: 0x0= no support.
Core_debug_model_mmap11:8roRead-only0x4Indicates the type of embedded processor debug model that the processor supports: 0x4= Armv7 based model - memory mapped.
Secure_debug_model 7:4roRead-only0x0Indicates the type of secure debug model that the processor supports: 0x0= no support.
Core_debug_model_cp 3:0roRead-only0x0Indicates the type of applications processor debug model that the processor supports: 0x0= no support.