ID_ISAR0 (R5_DBG_0) Register Description
| Register Name | ID_ISAR0 |
|---|---|
| Offset Address | 0x0000000D40 |
| Absolute Address | 0x00FEBF0D40 (CORESIGHT_R5_DBG_0) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x02101111 |
| Description | ISA Feature Register 0 |
ID_ISAR0 (R5_DBG_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Divide | 27:24 | roRead-only | 0x2 | Indicates support for divide instr. 0x2= Support for UDIV and SDIV in the Arm and Thumb ISA. Applies from Cortex-R5, r1p0. |
| Debug | 23:20 | roRead-only | 0x1 | Indicates support for debug instructions. 0x1= the processor supports BKPT. |
| Coprocessor | 19:16 | roRead-only | 0x0 | Indicates support for coprocessor instructions other than separately attributed feature registers, such as CP15 registers and VFP. 0x0= no support. |
| Compare_and_branch | 15:12 | roRead-only | 0x1 | Indicates support for combined compare and branch instructions. 0x1= the processor supports combinedcompare and branch instructions, CBNZand CBZ. |
| Bitfield | 11:8 | roRead-only | 0x1 | Indicates support for bitfield instructions. 0x1= the processor supportsbitfield instructions, BFC, BFI, SBFX, and UBFX. |
| Bit_counting | 7:4 | roRead-only | 0x1 | Indicates support for bit counting instructions. 0x1= the processor supports CLZ. |
| Atomic | 3:0 | roRead-only | 0x1 | Indicates support for atomic loadand store instructions. 0x1= the processor supports SWPand SWPB. |