ID_ISAR1 (R5_DBG_1) Register Description
| Register Name | ID_ISAR1 |
|---|---|
| Offset Address | 0x0000000D44 |
| Absolute Address | 0x00FEBF2D44 (CORESIGHT_R5_DBG_1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x13112111 |
| Description | ISA Feature Register 1 |
ID_ISAR1 (R5_DBG_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Jazelle | 31:28 | roRead-only | 0x1 | Indicates support for Jazelle instructions. 0x1= the processor supports: . BXJ instruction . J bit in PSRs |
| Interworking | 27:24 | roRead-only | 0x3 | Indicates support for interworking instructions. 0x3= the processor supports: . BX, and T bit in PSRs . BLX, and PC loads have BX behavior . Data-processing instr in the Arm instruction set with the PC as the destination and the S bit clear have BX-like behavior |
| Immediate | 23:20 | roRead-only | 0x1 | Indicates support for immediate instructions. 0x1= the processor supports: . the MOVT instruction . MOV instruction encodings with 16-bit immediates . Thumb ADD and SUB instr with 12-bit immediates |
| ITE | 19:16 | roRead-only | 0x1 | Indicates support for if then instructions. 0x1= the processor supports ITinstructions |
| Extend | 15:12 | roRead-only | 0x2 | Indicates support for sign or zero extend instructions. 0x2= the processor supports: . SXTB, SXTB16, SXTH, UXTB, UXTB16, and UXTH . SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, and UXTAH |
| Exception_2 | 11:8 | roRead-only | 0x1 | Indicates support for exception 2 instructions. 0x1= the processor supports: RFE, SRS, and CPS |
| Exception_1 | 7:4 | roRead-only | 0x1 | Indicates support for exception 1 instructions. 0x1= the processor supports: LDM(exception return), LDM(user registers), and STM(user registers). |
| Endian | 3:0 | roRead-only | 0x1 | Indicates support for endianness control instructions. 0x1= the processor supports: SETENDand E bit in PSRs |