ID_ISAR2 (R5_DBG_0) Register Description
| Register Name | ID_ISAR2 |
|---|---|
| Offset Address | 0x0000000D48 |
| Absolute Address | 0x00FEBF0D48 (CORESIGHT_R5_DBG_0) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x21232141 |
| Description | ISA Feature Register 2 |
ID_ISAR2 (R5_DBG_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reversal | 31:28 | roRead-only | 0x2 | Indicates support for reversal instructions. 0x2= the processor supports REV, REV16, REVSH, and RBIT. |
| PSR | 27:24 | roRead-only | 0x1 | Indicates support for PSRinstructions. 0x1= the processor supports MRSand MSR, and the exception return forms of data-processing instructions. |
| Unsigned_multiply | 23:20 | roRead-only | 0x2 | Indicates support for advanced unsigned multiply instructions. 0x2= the processor supports: . UMULL and UMLAL . UMAAL |
| Signed_multiply | 19:16 | roRead-only | 0x3 | Indicates support for advancedsigned multiply instructions. 0x3= the processor supports: . SMULL and SMLAL . SMLABB, SMLABT, SMLALBB,SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, and Q flag in PSRs . SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMPUL, SMPULR, SMUAD, SMUADX, SMUSD, and SMUSDX |
| Multiply | 15:12 | roRead-only | 0x2 | Indicates support for multiply instructions. 0x2= the processor supports MUL, MLA, and MLS. |
| Interruptible | 11:8 | roRead-only | 0x1 | Indicates support for multi-access interruptible instructions. 0x1= the processor supports restartable LDMand STM. |
| Memory_hint | 7:4 | roRead-only | 0x4 | Indicates support for memory hint instructions. 0x4= the processor supports PLD, PLIand PLDW. Applies from Cortex-R5, r1p0 |
| Load_store | 3:0 | roRead-only | 0x1 | Indicates support for additional load and store instructions. 0x1= the processor supports LDRDand STRD. |