ID_ISAR4 (R5_DBG_1) Register Description
| Register Name | ID_ISAR4 |
|---|---|
| Offset Address | 0x0000000D50 |
| Absolute Address | 0x00FEBF2D50 (CORESIGHT_R5_DBG_1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00010142 |
| Description | ISA Feature Register 4 |
ID_ISAR4 (R5_DBG_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| SWP_frac | 31:28 | roRead-only | 0x0 | RAZ because SWP/SWPB instruction support is indicated in ID_ISAR0. |
| PSR_M | 27:24 | roRead-only | 0x0 | Indicates support for M-profile instr for modifying the PSRs. 0x0= no support. |
| Exclusive | 23:20 | roRead-only | 0x0 | Indicates support for Exclusive instructions. 0x0= Only supports synchronization primitive instructionsas indicated by bits [15:12] in the ISAR3 register. |
| Barrier | 19:16 | roRead-only | 0x1 | Indicates support for Barrier instructions. 0x1= the processor supports DMB, DSB, and ISBinstructions. |
| SMC | 15:12 | roRead-only | 0x0 | Indicates support for Secure Monitor Call(SMC) (formerly SMI) instructions. 0x0= no support. |
| Write_back | 11:8 | roRead-only | 0x1 | Indicates support for write-back instructions. 0x1= supports all the writeback addressing modes defined in Armv7. |
| With_shift | 7:4 | roRead-only | 0x4 | Indicates support for with-shift instructions. 0x4= the processor supports: . the full range of constant shift options, on load/store and other instr . register-controlled shift options |
| Unprivileged | 3:0 | roRead-only | 0x2 | Indicates support for Unprivileged instructions. 0x2= the processor supports LDR{SB|B|SH|H}Tand STR{B|H}T. |