ID_MMFR0 (R5_DBG_0) Register Description
Register Name | ID_MMFR0 |
---|---|
Offset Address | 0x0000000D30 |
Absolute Address | 0x00FEBF0D30 (CORESIGHT_R5_DBG_0) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00210030 |
Description | Memory Model Feature Register 0 |
ID_MMFR0 (R5_DBG_0) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Innermost_shareability | 31:28 | roRead-only | 0x0 | Indicates the innermost shareability domain implemented. RAZ/Unknown because only oneshareability domain is implemented, see [15:12]. |
FCSE | 27:24 | roRead-only | 0x0 | Indicates support for Fast Context Switch Extension(FCSE). 0x0= no support. |
Auxiliary_Registers | 23:20 | roRead-only | 0x2 | Indicates support for the auxiliary registers. 0x2= the processor supports the Auxiliary Instruction and Data Fault Status Registers (AIFSR and ADFSR) and the Auxiliary Control Register. |
TCM_support | 19:16 | roRead-only | 0x1 | Indicates support for TCM and associated DMA. 0x1= implementation defined. |
Shareability_levels | 15:12 | roRead-only | 0x0 | Indicates the number of shareability levels implemented. 0x0= one level of shareability implemented |
Outermost_shareability | 11:8 | roRead-only | 0x0 | Indicates the outermost shareability domain implemented. 0x0= implemented as non-cacheable |
PMSA | 7:4 | roRead-only | 0x3 | Indicates support for Physical Memory System Architecture(PMSA). 0x3= the processor supports PMSAv7 (subsection support). |
VMSA | 3:0 | roRead-only | 0x0 | Indicates support for Virtual Memory System Architecture(VMSA). 0x0= no support. |