ID_MMFR0 (R5_DBG_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ID_MMFR0 (R5_DBG_0) Register Description

Register NameID_MMFR0
Offset Address0x0000000D30
Absolute Address 0x00FEBF0D30 (CORESIGHT_R5_DBG_0)
Width32
TyperoRead-only
Reset Value0x00210030
DescriptionMemory Model Feature Register 0

ID_MMFR0 (R5_DBG_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Innermost_shareability31:28roRead-only0x0Indicates the innermost shareability domain implemented.
RAZ/Unknown because only oneshareability domain is implemented, see [15:12].
FCSE27:24roRead-only0x0Indicates support for Fast Context Switch Extension(FCSE).
0x0= no support.
Auxiliary_Registers23:20roRead-only0x2Indicates support for the auxiliary registers.
0x2= the processor supports the Auxiliary Instruction and Data Fault Status Registers (AIFSR and ADFSR) and the Auxiliary Control Register.
TCM_support19:16roRead-only0x1Indicates support for TCM and associated DMA.
0x1= implementation defined.
Shareability_levels15:12roRead-only0x0Indicates the number of shareability levels implemented.
0x0= one level of shareability implemented
Outermost_shareability11:8roRead-only0x0Indicates the outermost shareability domain implemented.
0x0= implemented as non-cacheable
PMSA 7:4roRead-only0x3Indicates support for Physical Memory System Architecture(PMSA).
0x3= the processor supports PMSAv7 (subsection support).
VMSA 3:0roRead-only0x0Indicates support for Virtual Memory System Architecture(VMSA).
0x0= no support.