ID_MMFR1 (R5_DBG_0) Register Description
| Register Name | ID_MMFR1 |
|---|---|
| Offset Address | 0x0000000D34 |
| Absolute Address | 0x00FEBF0D34 (CORESIGHT_R5_DBG_0) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Memory Model Feature Register 1 |
ID_MMFR1 (R5_DBG_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Branch_predictor | 31:28 | roRead-only | 0x0 | Indicates BranchPredictor management requirements. 0x0= no MMU present. |
| L1_test_clean_op | 27:24 | roRead-only | 0x0 | Indicates support for test and clean op on data cache, Harvard or unified architecture. 0x0= no support. |
| L1_cache_maint_op_uni | 23:20 | roRead-only | 0x0 | Indicates support for L1 cache, entire cache maint op, uni architecture. 0x0= no support. |
| L1_cache_maint_op_Har | 19:16 | roRead-only | 0x0 | Indicates support for L1 cache, entire cache maint op, Harvard architecture. 0x0= no support. |
| L1_cache_line_maint_op_SnW_uni | 15:12 | roRead-only | 0x0 | Indicates support for L1 cache line maint op by Set and Way, uni architecture. 0x0= no support. |
| L1_cache_line_maint_op_SnW_Har | 11:8 | roRead-only | 0x0 | Indicates support for L1 cache line maint op by Set and Way, Harvard architecture. 0x0= no support. |
| L1_cache_line_maint_op_MVA_uni | 7:4 | roRead-only | 0x0 | Indicates support for L1 cache line maint op by address,uni architecture. 0x0= no support. |
| L1_cache_line_maint_op_MVA_Har | 3:0 | roRead-only | 0x0 | Indicates support for L1 cache line maint op by address, Harvard architecture. 0x0= no support. |