ID_MMFR2 (R5_DBG_1) Register Description
Register Name | ID_MMFR2 |
---|---|
Offset Address | 0x0000000D38 |
Absolute Address | 0x00FEBF2D38 (CORESIGHT_R5_DBG_1) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x01200000 |
Description | Memory Model Feature Register 2 |
ID_MMFR2 (R5_DBG_1) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
HW_access_flag | 31:28 | roRead-only | 0x0 | Indicates support for Hardware Access Flag. 0x0= no support. |
WFI | 27:24 | roRead-only | 0x1 | Indicates support for Wait-For-Interrupt stalling. 0x1= the processor supports Wait-For-Interrupt. |
Memory_barrier | 23:20 | roRead-only | 0x2 | Indicates support for memory barrier op. 0x2= the processor supports: . DSB (formerly DWB) . ISB (formerly Prefetch Flush) . DMB |
TLB_maint_op_uni | 19:16 | roRead-only | 0x0 | Indicates support for TLB maintenance operations, unified architecture. 0x0= no support. |
TLB_maint_op_Har | 15:12 | roRead-only | 0x0 | Indicates support for TLB maintenance operations, Harvard architecture. 0x0= no support. |
L1_cache_maint_range_op_Har | 11:8 | roRead-only | 0x0 | Indicates support for cache maintenance range operations, Harvard architecture. 0x0= no support. |
L1_bgnd_prefetch_cache_op | 7:4 | roRead-only | 0x0 | Indicates support for background prefetch cache range operations, Harvard architecture. 0x0= no support. |
L1_fgnd_prefetch_cache_op | 3:0 | roRead-only | 0x0 | Indicates support for foreground prefetch cache range operations, Harvard architecture. 0x0= no support. |