ID_MMFR2 (R5_DBG_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ID_MMFR2 (R5_DBG_1) Register Description

Register NameID_MMFR2
Offset Address0x0000000D38
Absolute Address 0x00FEBF2D38 (CORESIGHT_R5_DBG_1)
Width32
TyperoRead-only
Reset Value0x01200000
DescriptionMemory Model Feature Register 2

ID_MMFR2 (R5_DBG_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
HW_access_flag31:28roRead-only0x0Indicates support for Hardware Access Flag.
0x0= no support.
WFI27:24roRead-only0x1Indicates support for Wait-For-Interrupt stalling.
0x1= the processor supports Wait-For-Interrupt.
Memory_barrier23:20roRead-only0x2Indicates support for memory barrier op.
0x2= the processor supports:
. DSB (formerly DWB)
. ISB (formerly Prefetch Flush)
. DMB
TLB_maint_op_uni19:16roRead-only0x0Indicates support for TLB maintenance operations, unified architecture.
0x0= no support.
TLB_maint_op_Har15:12roRead-only0x0Indicates support for TLB maintenance operations, Harvard architecture.
0x0= no support.
L1_cache_maint_range_op_Har11:8roRead-only0x0Indicates support for cache maintenance range operations, Harvard architecture.
0x0= no support.
L1_bgnd_prefetch_cache_op 7:4roRead-only0x0Indicates support for background prefetch cache range operations, Harvard architecture.
0x0= no support.
L1_fgnd_prefetch_cache_op 3:0roRead-only0x0Indicates support for foreground prefetch cache range operations, Harvard architecture.
0x0= no support.