ID_MMFR3 (R5_DBG_1) Register Description
| Register Name | ID_MMFR3 |
|---|---|
| Offset Address | 0x0000000D3C |
| Absolute Address | 0x00FEBF2D3C (CORESIGHT_R5_DBG_1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000211 |
| Description | Memory Model Feature Register 3 |
ID_MMFR3 (R5_DBG_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:20 | roRead-only | 0x0 | RAZ because this is a PMSA implementation. |
| Maint_broadcast | 15:12 | roRead-only | 0x0 | Indicates whether cache maint op are broadcast. 0x0= cache maintenance operations only affect local structures. |
| Branch_predictor_maint_op | 11:8 | roRead-only | 0x2 | Indicates support for branch predictor maintenance operations in systems with hierarchical cache maintenance operations. 0x2= supports invalidate entire branch predictor array and invalidate branch predictor by MVA |
| Hier_cache_maint_by_SnW | 7:4 | roRead-only | 0x1 | Indicates support for hierarchical cache maintenance operations by Set and Way. 0x1= the processor supports invalidate cache,clean and invalidate, and clean by Set and Way. |
| Hier_cache_maint_by_MVA | 3:0 | roRead-only | 0x1 | Indicates support for hierarchical cache maintenance operations by address. 0x1= the processor supports: . Invalidate data cache by address . Clean data cache by address . Clean and invalidate data cache by address . Invalidate instruction cache by address . Invalidate all instruction cache entries |