ID_PFR0 (R5_DBG_0) Register Description
| Register Name | ID_PFR0 |
|---|---|
| Offset Address | 0x0000000D20 |
| Absolute Address | 0x00FEBF0D20 (CORESIGHT_R5_DBG_0) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000131 |
| Description | Processor Feature Register 0 |
ID_PFR0 (R5_DBG_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| State3 | 15:12 | roRead-only | 0x0 | Indicates support for Thumb Execution Environment (ThumbEE). 0x0= no support. |
| State2 | 11:8 | roRead-only | 0x1 | Indicates support for acceleration of execution environments in hardware or software. 0x1= the processor supports acceleration ofexecution environments in software. |
| State1 | 7:4 | roRead-only | 0x3 | Indicates type of Thumb encoding that the processor supports. 0x3= the processor supports Thumb encoding with all Thumb instructions. |
| State0 | 3:0 | roRead-only | 0x1 | Indicates support for Arm instruction set. 0x1= the processor supports Arm instructions. |