ID_PFR1 (R5_DBG_1) Register Description
| Register Name | ID_PFR1 |
|---|---|
| Offset Address | 0x0000000D24 |
| Absolute Address | 0x00FEBF2D24 (CORESIGHT_R5_DBG_1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000001 |
| Description | Processor Feature Register 1 |
ID_PFR1 (R5_DBG_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| uCtlr_prog_model | 11:8 | roRead-only | 0x0 | Indicates support for Microcontroller programmers model: 0x0= no support. |
| Security_extension | 7:4 | roRead-only | 0x0 | Indicates support for Security Extensions architecture: 0x0= no support. |
| Armv4_prog_model | 3:0 | roRead-only | 0x1 | Indicates support for standard Armv4 programmers model: 0x1= the processor supports the Armv4 model. |