IER (APMDDR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

IER (APMDDR) Register Description

Register NameIER
Offset Address0x0000000034
Absolute Address 0x00FD0B0034 (APM_DDR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionInterrupt Enable

0: Disabled 1: Enabled.

IER (APMDDR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MET_CT9_OVFLINT_EN12rwNormal read/write0x0Metric Counter 9 Overflow Interrupt.
MET_CT8_OVFLINT_EN11rwNormal read/write0x0Metric Counter 8 Overflow Interrupt.
MET_CT7_OVFLINT_EN10rwNormal read/write0x0Metric Counter 7 Overflow Interrupt.
MET_CT6_OVFLINT_EN 9rwNormal read/write0x0Metric Counter 6 Overflow Interrupt.
MET_CT5_OVFLINT_EN 8rwNormal read/write0x0Metric Counter 5 Overflow Interrupt.
MET_CT4_OVFLINT_EN 7rwNormal read/write0x0Metric Counter 4 Overflow Interrupt.
MET_CT3_OVFLINT_EN 6rwNormal read/write0x0Metric Counter 3 Overflow Interrupt.
MET_CT2_OVFLINT_EN 5rwNormal read/write0x0Metric Counter 2 Overflow Interrupt.
MET_CT1_OVFLINT_EN 4rwNormal read/write0x0Metric Counter 1 Overflow Interrupt.
MET_CT0_OVFLINT_EN 3rwNormal read/write0x0Metric Counter 0 Overflow Interrupt.
SMPL_INTRVL_OVFLINT_EN 1rwNormal read/write0x0Sample Interval Counter Overflow Interrupt.
GLBCLKCNT_OVFLINT_EN 0rwNormal read/write0x0Global Clock Counter Overflow Interrupt.