IMR (XMPU_DDR) Register Description
| Register Name | IMR |
|---|---|
| Offset Address | 0x0000000014 |
| Absolute Address |
0x00FD000014 (DDR_XMPU0_CFG) 0x00FD010014 (DDR_XMPU1_CFG) 0x00FD020014 (DDR_XMPU2_CFG) 0x00FD030014 (DDR_XMPU3_CFG) 0x00FD040014 (DDR_XMPU4_CFG) 0x00FD050014 (DDR_XMPU5_CFG) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x0000000F |
| Description | Interrupt Mask. |
0: enabled. 1: masked (disabled). If the ISR bit = 1 (asserted interrupt) and the IMR bit = 0 (not masked), then the IRQ to the interrupt controller is asserted. Software checks the ISR to determine the cause of the interrupt. Read-only.
IMR (XMPU_DDR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:4 | roRead-only | 0x0 | reserved |
| SecurityVIO | 3 | roRead-only | 0x1 | Security violation by AXI master. |
| WrPermVIO | 2 | roRead-only | 0x1 | Write permission violation by AXI master. |
| RdPermVIO | 1 | roRead-only | 0x1 | Read permission violation by AXI master. |
| INV_APB | 0 | roRead-only | 0x1 | Register Access Error on APB. |