INIT0 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

INIT0 (DDRC) Register Description

Register NameINIT0
Offset Address0x00000000D0
Absolute Address 0x00FD0700D0 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x0002004E
DescriptionSDRAM Initialization Register 0

All register fields are static, unless described otherwise in the register field description. Static registers can only be written when the controller is in reset.

INIT0 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
skip_dram_init31:30rwNormal read/write0x0If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed
- 00 - SDRAM Initialization routine is run after power-up
- 01 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Normal Mode
- 11 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Self-refresh Mode
- 10 - SDRAM Initialization routine is run after power-up.
Note: The only 2b00 is supported for LPDDR4 in this version of the DDRC.
Programming Mode: Quasi-dynamic Group 2
post_cke_x102425:16rwNormal read/write0x2Cycles to wait after driving CKE high to start the SDRAM initialization sequence.
Unit: 1024 clocks.
LPDDR3 typically requires this to be programmed for a delay of 200us.
LPDDR4 typically requires this to be programmed for a delay of 2us.
Program this to JEDEC spec value divided by 2, and round it up to next integer value.
pre_cke_x102411:0rwNormal read/write0x4ECycles to wait after reset before driving CKE high to start the SDRAM initialization sequence.
Unit: 1024 clock cycles.
LPDDR3: tINIT1 of 100 ns (min)
LPDDR4: tINIT3 of 2 ms (min)
Program this to JEDEC spec value divided by 2, and round it up to next integer value.