INIT2 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

INIT2 (DDRC) Register Description

Register NameINIT2
Offset Address0x00000000D8
Absolute Address 0x00FD0700D8 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000005
DescriptionSDRAM Initialization Register 2

This register is static. Static registers can only be written when the controller is in reset.

INIT2 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
min_stable_clock_x1 3:0rwNormal read/write0x5Time to wait after the first CKE high, tINIT2.
Unit: 1 clock cycle.
LPDDR3 typically requires 5 x tCK delay.