INIT2 (DDRC) Register Description
Register Name | INIT2 |
---|---|
Offset Address | 0x00000000D8 |
Absolute Address | 0x00FD0700D8 (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000005 |
Description | SDRAM Initialization Register 2 |
This register is static. Static registers can only be written when the controller is in reset.
INIT2 (DDRC) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
min_stable_clock_x1 | 3:0 | rwNormal read/write | 0x5 | Time to wait after the first CKE high, tINIT2. Unit: 1 clock cycle. LPDDR3 typically requires 5 x tCK delay. |