INIT5 (DDRC) Register Description
Register Name | INIT5 |
---|---|
Offset Address | 0x00000000E4 |
Absolute Address | 0x00FD0700E4 (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00100004 |
Description | SDRAM Initialization Register 5 |
This register is static. Static registers can only be written when the controller is in reset.
INIT5 (DDRC) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
dev_zqinit_x32 | 23:16 | rwNormal read/write | 0x10 | ZQ initial calibration, tZQINIT. Unit: 32 clock cycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR3 requires 1us. |
max_auto_init_x1024 | 9:0 | rwNormal read/write | 0x4 | Maximum duration of the auto initialization, tINIT5. LPDDR3 typically requires 10us. |