INIT5 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

INIT5 (DDRC) Register Description

Register NameINIT5
Offset Address0x00000000E4
Absolute Address 0x00FD0700E4 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00100004
DescriptionSDRAM Initialization Register 5

This register is static. Static registers can only be written when the controller is in reset.

INIT5 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dev_zqinit_x3223:16rwNormal read/write0x10ZQ initial calibration, tZQINIT.
Unit: 32 clock cycles.
DDR3 typically requires 512 clocks.
DDR4 requires 1024 clocks.
LPDDR3 requires 1us.
max_auto_init_x1024 9:0rwNormal read/write0x4Maximum duration of the auto initialization, tINIT5.
LPDDR3 typically requires 10us.