INIT6_SHADOW (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

INIT6_SHADOW (DDRC) Register Description

Register NameINIT6_SHADOW
Offset Address0x00000020E8
Absolute Address 0x00FD0720E8 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSDRAM Initialization Shadow Register 6

All register fields are quasi-dynamic group 2 and group 4, unless described otherwise in the register field description. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.

INIT6_SHADOW (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
mr431:16rwNormal read/write0x0DDR4- Value to be loaded into SDRAM MR4 registers.
Used in DDR4 designs only.
mr515:0rwNormal read/write0x0DDR4- Value to be loaded into SDRAM MR5 registers.
Used in DDR4 designs only.
Programming Mode: Quasi-dynamic Group 1 and Group 4