INTENCLR_EL1 (A53_PMU_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

INTENCLR_EL1 (A53_PMU_3) Register Description

Register NameINTENCLR_EL1
Offset Address0x0000000C60
Absolute Address 0x00FEF30C60 (CORESIGHT_A53_PMU_3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPerformance Monitors Interrupt Enable Clear Register

INTENCLR_EL1 (A53_PMU_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
C31rwNormal read/write0x0PMCCNTR_EL0 overflow interrupt request disable bit.
P30:0rwNormal read/write0x0Event counter overflow interrupt request disable bit for EVCNTR<x>_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: