INTENSET_EL1 (A53_PMU_0) Register Description
Register Name | INTENSET_EL1 |
---|---|
Offset Address | 0x0000000C40 |
Absolute Address | 0x00FEC30C40 (CORESIGHT_A53_PMU_0) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Performance Monitors Interrupt Enable Set Register |
INTENSET_EL1 (A53_PMU_0) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
C | 31 | rwNormal read/write | 0x0 | PMCCNTR_EL0 overflow interrupt request enable bit. |
P | 30:0 | rwNormal read/write | 0x0 | Event counter overflow interrupt request enable bit for EVCNTR<x>_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: |