IOPLL_FRAC_CFG (CRL_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

IOPLL_FRAC_CFG (CRL_APB) Register Description

Register NameIOPLL_FRAC_CFG
Offset Address0x0000000028
Absolute Address 0x00FF5E0028 (CRL_APB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionFractional control for the PLL

IOPLL_FRAC_CFG (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ENABLED31rwNormal read/write0x0Fractional SDM bypass control.
0: PLL is in integer mode and it ignores all fractional data.
1: PLL is in fractional mode and uses [DATA] bitfield for the fractional portion of the feedback divider.
DATA15:0rwNormal read/write0x0Fractional value for the Feedback value.