IOPLL_TO_FPD_CTRL (CRL_APB) Register Description
Register Name | IOPLL_TO_FPD_CTRL |
Offset Address | 0x0000000044 |
Absolute Address |
0x00FF5E0044 (CRL_APB)
|
Width | 16 |
Type | rwNormal read/write |
Reset Value | 0x00000400 |
Description | IOPLL clock divider for distribution in FPD. |
Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock generators.
IOPLL_TO_FPD_CTRL (CRL_APB) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
Reserved | 15:14 | rwNormal read/write | 0x0 | reserved |
DIVISOR0 | 13:8 | rwNormal read/write | 0x4 | 6-bit divider. |
Reserved | 7:0 | rwNormal read/write | 0x0 | reserved |