IR_STATUS (CRF_APB) Register Description
| Register Name | IR_STATUS |
|---|
| Offset Address | 0x0000000004 |
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| Absolute Address |
0x00FD1A0004 (CRF_APB)
|
|---|
| Width | 1 |
|---|
| Type | wtcReadable, write a 1 to clear |
|---|
| Reset Value | 0x00000000 |
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| Description | APB Register Address Decode Error Interrupt Status and Clear. |
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Access Violation. READ: 0: no interrupt. 1: interrupt flagged. WRITE: 0: no effect. 1: clear bit to 0. Once flagged, the interrrupt bit stays set until cleared with a write of 1. If a Status bit is 1 and its Mask is 0 (enabled), then the IRQ interrupt signal is active to the interrupt controllers.
IR_STATUS (CRF_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| addr_decode_err | 0 | wtcReadable, write a 1 to clear | 0x0 | Register Access Decode Error on APB interface. |