ISR (APMDDR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

ISR (APMDDR) Register Description

Register Name	ISR
Offset Address	0x0000000038
Absolute Address	0x00FD0B0038 (APM_DDR)
Width	32
Type	rwNormal read/write
Reset Value	0x00000000
Description	Interrupt Status

0: Not Active 1: Active.

ISR (APMDDR) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
MET_CT9_OVFLINT	12	rwNormal read/write	0x0	Metric Counter 9 Overflow Interrupt.
MET_CT8_OVFLINT	11	rwNormal read/write	0x0	Metric Counter 8 Overflow Interrupt.
MET_CT7_OVFLINT	10	rwNormal read/write	0x0	Metric Counter 7 Overflow Interrupt.
MET_CT6_OVFLINT	9	rwNormal read/write	0x0	Metric Counter 6 Overflow Interrupt.
MET_CT5_OVFLINT	8	rwNormal read/write	0x0	Metric Counter 5 Overflow Interrupt.
MET_CT4_OVFLINT	7	rwNormal read/write	0x0	Metric Counter 4 Overflow Interrupt.
MET_CT3_OVFLINT	6	rwNormal read/write	0x0	Metric Counter 3 Overflow Interrupt.
MET_CT2_OVFLINT	5	rwNormal read/write	0x0	Metric Counter 2 Overflow Interrupt.
MET_CT1_OVFLINT	4	rwNormal read/write	0x0	Metric Counter 1 Overflow Interrupt.
MET_CT0_OVFLINT	3	rwNormal read/write	0x0	Metric Counter 0 Overflow Interrupt.
SMPL_INTRVL_OVFLINT	1	rwNormal read/write	0x0	Sample Interval Counter Overflow Interrupt.
GLBCLKCNT_OVFLINT	0	rwNormal read/write	0x0	Global Clock Counter Overflow Interrupt.