ISR (APU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ISR (APU) Register Description

Register NameISR
Offset Address0x0000000010
Absolute Address 0x00FD5C0010 (APU)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionInterrupt Status Register

ISR (APU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
INV_APB 0wtcReadable, write a 1 to clear0x0APB (register) access occurs to an unimplemented space