ISR (XMPU_FPD) Register Description
| Register Name | ISR |
|---|---|
| Offset Address | 0x0000000010 |
| Absolute Address | 0x00FD5D0010 (FPD_XMPU_CFG) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt Status and Clear. |
AXI and APB Access Violations. READ: 0: no interrupt request. 1: interrupt requested. WRITE: 0: no effect. 1: clear bit to 0. If a Status bit is 1 and its Mask is 0, then the IRQ interrupt signal is activated to the interrupt controller. The first AXI violation is recorded. Once an ISR[3:1] status bit is set, subsequent AXI violations are not recorded, but their transactions are poisoned. The status bits are cleared by a system reset and can be cleared by software.
ISR (XMPU_FPD) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:4 | roRead-only | 0x0 | reserved |
| SecurityVIO | 3 | wtcReadable, write a 1 to clear | 0x0 | Security Violation by AXI Master. Two conditions can cause a security violation: 1) A non-secure master tries to access a secure memory space. 2) A secure master tries to access a non-secure memory space and Rxx_CONFIG [NSCheckType] = 1 (strict checking). Note: a secure transaction is detected when AxPROT[1] = 0. |
| WrPermVIO | 2 | wtcReadable, write a 1 to clear | 0x0 | Write Permission Violation by AXI Master. Write access attempted to enabled region with WrAllowed = 0. Or the transaction missed in the Region list and CNTRL [DefWrAllowed] = 0. |
| RdPermVIO | 1 | wtcReadable, write a 1 to clear | 0x0 | Read Permission Violation by AXI Master. Read access attempted to enabled region with RdAllowed = 0. Or the transaction missed in the Region list and CNTRL [DefRdAllowed] = 0. |
| INV_APB | 0 | wtcReadable, write a 1 to clear | 0x0 | Register Access Error on APB. A register access was requested to an unimplemented register location. The PSLVERR error signal is also asserted back to the APB interconnect. |